This commit is contained in:
Vinicius Silva 2024-07-12 12:02:29 -03:00
parent c3ff7ea4aa
commit c029e81e89
9 changed files with 198 additions and 14 deletions

26
main.py Normal file
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@ -0,0 +1,26 @@
import random
number_of_bits = input('Type the number of bits\n')
instruction = ''
rand = random.Random(100)
rand.seed(100)
bits = ['0','1']
bit_instruction = []
i = 0
while i < number_of_bits:
instruction += bits[rand.randint() % 2]
i += 1
intervals_list = input('Type intervals\n').split(" ")
intervals = list(map(eval, intervals_list))
for interval in intervals:
bit_instruction.append(instruction[31-interval[0], 31-(interval[1]+1)])

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@ -3,7 +3,7 @@ module main
import vm
import readline
mut kernel := none
__global kernel = none
fn start_kernel(){
kernel = Kernel{}

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@ -2,7 +2,7 @@ module main
import kernel as os
cmds := {
syscalls := {
'EXIT' : 0
'READ' : 1
'WRITE' : 2

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@ -1,4 +1,68 @@
fn start_assembler()
{
import kernel as os
__global mneumonics = {
// Menumonic : [TYPE | ( OPCODE, FUNC3, (FUNC7 | IMM) )]
'ADD' : [0x33, 0x0],
'SUB' : [0x33, 0x0],
'XOR' : [0x33, 0x4],
'OR' : [0x33, 0x6],
'AND' : [0x33, 0x7],
'SLL' : [0x33, 0x1],
'SRL' : [0x33, 0x5],
'SRA' : [0x33, 0x5],
'SLT' : [0x33, 0x2],
'SLTU' : [0x33, 0x3],
'ADDI' : [0x13, 0x0],
'XORI' : [0x13, 0x4],
'ORI' : [0x33, 0x6],
'ANDI' : [0x13, 0x7],
'SLLI' : [0x13, 0x1],
'SRLI' : [0x33, 0x5],
'SRAI' : [0x13, 0x5],
'SLTI' : [0x13, 0x2],
'SLTIU' : [0x13, 0x3],
'LB' : [0x03, 0x0],
'LH' : [0x03, 0x1],
'LW' : [0x03, 0x2],
'LBU' : [0x03, 0x4],
'LHU' : [0x03, 0x5],
'SB' : [0x23, 0x0],
'SH' : [0x23, 0x1],
'SW' : [0x23, 0x2],
'BEQ' : [0x63, 0x0],
'BNE' : [0x63, 0x1],
'BLT' : [0x63, 0x4],
'BGE' : [0x63, 0x5],
'BLTU' : [0x63, 0x6],
'BGEU' : [0x63, 0x7],
'JAL' : [0x6F, 0x0],
'JALR' : [0x67, 0x0],
'LUI' : [0x37],
'AUIPC' : [0x17],
'ECALL' : [0x73, 0x0, 0x0],
'EBREAK': [0x73, 0x0, 0x1],
}
__global registers = {
}
fn bytecode(asm_buffer [u8])
{
mut asm_instruction := asm_buffer.pop()
mut mneumonic := asm_instruction.split(' ')[0].to_upper()
bytecodes := mneumonics[mneumonic]
mut opcode := bytecodes[0]
mut func3 := bytecodes[1]
mut func7_or_imm := bytecodes[2]
}
fn start_assembler()
{
assert os.kernel != none
for{ if kernel.stdin.len != 0 { bytecode(&kernel.stdin) } }
}

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@ -72,8 +72,8 @@ fn (cpu CPU) decode(u32 instruction)
0x33 {
mut funct3 := (instruction & 0x7000) >> 12
mut rd := (instruction & 0x7000) >> 12
mut funct3 := (instruction & 0xA80) >> 7
mut rd :=
mut rs1 :=
mut rs2 :=
mut funct7 :=

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@ -2,8 +2,7 @@ module main
import cpu
mut hardware := Hardware{ram: RAM{}, cpu: Cpu{}}
mut vm_hardwares := Hardware{ram: RAM{}, cpu: Cpu{}}
struct Hardware
{
@ -12,7 +11,6 @@ struct Hardware
cpu cpu.CPU;
}
struct RAM
{
pub:
@ -23,8 +21,6 @@ struct RAM
current_memory_addess u32
}
fn load_instructions(asm_instructions[string])
{
for mut instruction in asm_instructions {
@ -39,8 +35,6 @@ fn start_assembler()
fn start_vm()
{
// Load asm instructions, converts to machine instructions and save in memory
start_assembler()
// Get in memory, decode and run instructions
@ -49,4 +43,5 @@ fn start_vm()
threads << spawn cpu.start_cpu()
threads << spawn os.boot()
thread << spawn start_asembler()
}

BIN
test Executable file

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62
test.v Normal file
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@ -0,0 +1,62 @@
import os
__global t = []string{}
__global is_finish = false
__global is_cpu_started = false
__global is_os_booted = false
__global threads = []thread{}
fn start_cpu(){
mut pc := 0
if !is_cpu_started { println("STARTING CPU...") }
for{
if t.len != 0 && is_finish {
println("LOADING INSTRUCTIONS...")
mut c := t.pop()
}else if t.len == 0 && is_finish{
is_finish = false
}
}
}
fn sh(){
mut pc := 0
if !is_os_booted { println("BOOTING OPERATING SYSTEM...") }
println("=================================================================")
println(" WELCOME TO VINUX ")
println("=================================================================")
for{
mut str := os.input('# ')
if str == 'EXIT' {
exit(0)
} else if str != 'END' {
t << str
}else{
is_finish = true
}
}
}
fn main(){
mut first := false
for {
is_cpu_started = true
threads << spawn start_cpu()
is_os_booted = true
threads << spawn sh()
threads.wait()
}
}

37
test.vsh Normal file
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@ -0,0 +1,37 @@
import readline
mut t := []string{}
fn start_cpu(){
mut pc := 0
for{
if t.len != 0 {
print(t[pc])
pc++;
}
}
}
fn start_mem(){
read := readline.Readline{}
mut pc := 0
for{
mut str := read.read_line()
t << str
}
}
fn main(){
mut threads := []thread{}
threads << spawn start_cpu()
threads << spawn start_mem()
thread.wait()
}